(1) Field of the Invention
The present invention relates to a constant on time controller, and more particularly relates to a constant on time controller for deciding a constant on-time period according to a bootstrap voltage.
(2) Description of the Prior Art
FIG. 1 is a schematic diagram of a conventional buck converting circuit and a constant on time controller. The buck converting circuit comprises a high-side transistor M1, a low-side transistor M2, an inductance L and a capacitance C. The high-side transistor M1 is coupled between an input voltage Vin and a switching node, and the low-side transistor M2 is coupled between the switching node and a ground potential. The inductance L and the capacitance C are connected in series between the switching node and the ground potential for filtering a voltage of the switching node into an output voltage Vout. The constant on time controller controls the switchings of the high-side transistor M1 and the low-side transistor M2 of the buck converting circuit, and a duty cycle of the high-side transistor M1 decides a ratio of the output voltage Vout to the input voltage Vin.
The constant on time controller comprises comparators 8 and 10, a SR flip-flop 9, a capacitance 11, a transistor 12, a resistance 13 and a driving circuit 19. One terminal of the resistance 13 is connected to the input voltage Vin, and another terminal thereof is connected to the capacitance 11. A non-inverting terminal of the comparator 8 and an inverting terminal of the comparator 10 receive a reference voltage Vref. An inverting terminal of the comparator 8 receives the output voltage Vout, and triggers a set terminal S of the SR flip-flop 9 when the output voltage Vout is lower than the reference voltage Vref for enabling the SR flip-flop 9 to generate a high level signal at an output terminal Q. At this moment, the driving circuit 19 turns on the high-side transistor M1 and cuts off the low-side transistor M2. At the same time, the SR flip-flop 9 generates a low level signal at an inverting output terminal Q to cut off the transistor 12. The capacitance 11 starts to be charged at this time. When a voltage of the capacitance 11 is raised to the reference voltage Vref, the comparator 10 outputs the high level signal to a reset terminal R of the SR flip-flop 9 for enabling the SR flip-flop 9 to output a low level signal at the output terminal Q and a high level signal at the inverting output terminal V. At this moment, the driving circuit 19 cuts off the high-side transistor M1 and turns on the low-side transistor M2. Besides, the transistor 12 is simultaneously turned on to discharge the capacitance 11 to zero through the transistor 12, so as to be ready for the output voltage Vout to be lower than the reference voltage Vref again. Thus, when the buck converting circuit is in a stable state, the output voltage Vout is substantially equal to the reference voltage Vref.
The aforementioned circuit uses the resistance 13 to generate a current proportional to the input voltage Vin for charging, the capacitance 11 to reach the output voltage Vout. Therefore, in each cycle, the charging time period of the capacitance 11 is proportional to the ratio of the output voltage Vout to the input voltage Vin, i.e., the constant on time period is proportional to the ratio of the output voltage Vout to the input voltage Vin.
However, the constant on time controller has to additionally add a pin connected to the input voltage Vin for obtaining the information of the input voltage Vin, thus increasing the packaging cost of the constant on time controller.